\begin{abstract}
Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling.
However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology.
In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation
that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to
satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a
cost-driven 3D design space optimization flow that balances the design area and metal layer requirement,
by optimizing the cost tradeoffs between silicon area and the number of metal layers.
With the cost-driven design optimization flow, We can achieve cost saving up to 19\% for TSV-based 3D designs,
and 26\% for interposer-based 3D designs, respectively, compared to the baseline designs.
\end{abstract}


\vspace{10pt}
\section{Introduction}\label{sec:intro}
Three-dimensional integrated circuit (3D IC) is a promising technology that benefits from both integration density and performance. By integrating a high-bandwidth low-latency vertical interconnects \emph{Through-Silicon Vias (TSVs)}, 3D integrations can provide: (i) smaller footprint and higher package density; (ii) higher performance and lower interconnect power consumption; (iii) heterogeneous chip stacking~\cite{yuan06, Davis2005, kinck2008}. 

The high fabrication cost of 3D stacking is a major concern for adopting this emerging technology. Different from 2D designs, 3D designs need wafer thinning and wafer bonding, implying higher process complexity and lower fabrication yield. Previous study shows that, a 2 layer 3D design is more cost efficient than the corresponding 2D design only when the design gate count is more than 143 million for 45nm process technology, making 3D integration not suitable for small designs~\cite{xiangyu2010}. Providing a cost-efficient design is an urgent requirement for 3D technology.

Mask cost is one important component in fabrication cost. Contemporary complex circuits require more metal layers, making the mask cost continuously increases. For example, at 32nm technology node, the number of process steps is 462 with mask cost of 2.974M/set for 9 metal layers; when the number of metal layers increases to 11, the process steps and mask cost increase to 498 and 3.212M/set, respectively~\cite{ICcostmodel}. Besides mask cost for metal layers, chip area is another determinant of fabrication cost due to its direct impact on yield. Reducing metal layers can cut down the process steps and mask cost, however, it will cause dramatic increment in chip size in 2D designs. By replacing long interconnects with TSVs in 3D designs, metal layers can be reduced while small chip size is maintained as shown in~\cite{xiangyu2010}. 

In this work, we implemented a block granularity 3D design optimization flow to generate cost-efficient designs by balancing the chip size (placement density) and routability (metal layers). At physical design stage, CAD tools require designers to input the area utilization for placement density. Thus, the design quality highly depends on the designers experience and circuit complexity. In this flow, optimal placement density and metal layer reduction are considered concurrently for cost-efficient designs. Both TSV-based 3D and interposer-based 3D designs are included in our work.

The rest of the paper is organized as follows: the background of TSV and interposer-based 3D ICs are introduced in Section~\ref{sec:bkground}; Section~\ref{sec:model} illustrates the interconnect model for routability and the 3D design cost model used in this work; the cost-driven 3D design optimization flow is demonstrated in Section~\ref{sec:mechanism}; the experimental setup and results are shown in Section~\ref{sec:experiment} following by conclusion in Section~\ref{sec:conclusion}. 